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Effect of Forward and Backward Compatibility of Solder Paste and Component Finish on Fine-Pitch Component Assemblies Using ENIG and IMAG PWB Finishes

[+] Author Affiliations
Anand Kannabiran, Sreekanth Varma Penmatsa, S. Manian Ramkumar

Rochester Institute of Technology, Rochester, NY

Reza Ghaffarian

California Institute of Technology, Pasadena, CA

Paper No. IPACK2007-33963, pp. 945-952; 8 pages
doi:10.1115/IPACK2007-33963
From:
  • ASME 2007 InterPACK Conference collocated with the ASME/JSME 2007 Thermal Engineering Heat Transfer Summer Conference
  • ASME 2007 InterPACK Conference, Volume 1
  • Vancouver, British Columbia, Canada, July 8–12, 2007
  • Conference Sponsors: Electronic and Photonic Packaging Division
  • ISBN: 0-7918-4277-0 | eISBN: 0-7918-3801-3
  • Copyright © 2007 by ASME

abstract

The primary objective of this experimental research is to understand the common issues faced in a manufacturing environment that assembles products containing a variety of fine-pitch devices. The testing phase of the research, relates to characterizing the thermo-mechanical integrity of surface mount mixed (Sn-Pb & lead-free) assembly solder joints. The investigation involves both forward and backward compatibility in electronics assemblies on Pb-free PWB surface finishes. A full factorial design is used in the investigation, with 3 factors — solder paste, component finish and PWB surface finish. Eutectic Sn-Pb paste (63–37% wt) and SAC305 (Sn 3.0%Ag0.5%Cu) paste are used as Pb-containing and Pb-free levels respectively. For component finish metallization, Sn-Pb termination finish/bump composition is used for Pb-containing level while Sn termination/SAC 405 bump composition represents the Pb-free level. Immersion Silver (ImAg) and Electroless Nickel Immersion Gold (ENIG) surface finish on printed wiring board (PWB) is used for testing and analysis. The testing was aimed at providing results for a wide variety of fine-pitch components commonly used in surface mount solder assemblies. Hence, a PWB containing flip chip (0.4mm pitch), Ultra chip scale package (UCSP), micro-lead frame (MLF) or quad flat pack no-lead (QFN), thin small outline package (TSOP −0.5 mm pitch) and plastic ball grid array (PBGA −1156 I/O and 256 I/O −1 mm pitch) devices was designed and used for testing. The test vehicle also includes resistors (0201, 0402 & 0603). The stencil thickness and openings were selected to accommodate both the large PBGA (1156 I/O) and finer pitch components. The reflow profile was designed taking into account the component maximum temperature exposure limitations, due to non-uniformity in heating, determined from thermocouples during initial assembly. Lessons learned from the design, reflow process optimization and manufacturing are presented in this paper. The solder joints were subjected to isothermal aging followed by mechanical shock test, attempting to establish a relationship between the intermetallic growth at the solder/PWB interface and the mechanical integrity of the solder joint. The compounding of test, unlike singular test methods, provides a more realistic estimate of the reliability and life of the joint in the field. The assemblies were cross-sectioned after the tests and the microstructure of the solder joints will be analyzed to study the intermetallic growth upon isothermal aging.

Copyright © 2007 by ASME

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