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Wiresweep Reduction via Direct Cavity Injection During Encapsulation of Stacked Chip-Scale Packages

[+] Author Affiliations
Jason M. Brand, Amip J. Shah

Intel Corporation, Folsom, CA

Salvatore A. Ruggero

Intel Corporation, Chandler, AZ

Paper No. IPACK2007-33044, pp. 887-894; 8 pages
doi:10.1115/IPACK2007-33044
From:
  • ASME 2007 InterPACK Conference collocated with the ASME/JSME 2007 Thermal Engineering Heat Transfer Summer Conference
  • ASME 2007 InterPACK Conference, Volume 1
  • Vancouver, British Columbia, Canada, July 8–12, 2007
  • Conference Sponsors: Electronic and Photonic Packaging Division
  • ISBN: 0-7918-4277-0 | eISBN: 0-7918-3801-3
  • Copyright © 2007 by ASME

abstract

As packaging continues to offer challenges with variable stacked die configurations of increasing complexity, traditional transfer mold encapsulation faces challenges in defining a robust process window. A major concern is the problem of “wiresweep”, wherein deformation of the wirebond during the mold process can potentially cause short-circuiting. Several prior studies have focused on qualifying the effects of various wirebond and mold process parameters on package wiresweep, but most of these studies are restricted to single (discrete) die packages. This paper attempts to fill this gap-of-knowledge by experimenting with a variety of test vehicles with different stacking configurations. Specifically, the effects of varying loop height, stack height and mold compound type are quantified in terms of maximum wiresweep. We find that loop height can have a considerable effect on wiresweep, with the maximum wiresweep being reduced by half (from around 6% to less than 3%) simply by reducing the loop height. Additionally, the study finds that for a given mold process, higher die stacks tend to increase wiresweep, although a threshold stack height exists beyond which further stacking can reduce wiresweep. Lastly, the data suggest that the choice of mold compound can adversely impact wiresweep, especially for test vehicles with traditionally high wiresweep. Having identified these trends, semi-analytical models from the literature are used to investigate the cause behind these observations. The analysis suggests that the mold front velocity has the major root impact on package wiresweep. To validate this hypothesis, the series of tests conducted earlier is repeated for a compression mold process which provides greater control over the mold front velocity. As predicted by the model, significant reduction in wiresweep is achieved. Thus, the compression mold process seems to offer the opportunity for reducing wiresweep without any compromise in the complexity of the die stack.

Copyright © 2007 by ASME

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