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Reliability Modeling of Lead Free Solder Joints in Wafer-Level Chip Scale Packages

[+] Author Affiliations
Jie-Hua Zhao, Vikas Gupta, Alok Lohia, Darvin Edwards

Texas Instruments Incorporated, Dallas, TX

Paper No. IPACK2007-33123, pp. 351-358; 8 pages
doi:10.1115/IPACK2007-33123
From:
  • ASME 2007 InterPACK Conference collocated with the ASME/JSME 2007 Thermal Engineering Heat Transfer Summer Conference
  • ASME 2007 InterPACK Conference, Volume 1
  • Vancouver, British Columbia, Canada, July 8–12, 2007
  • Conference Sponsors: Electronic and Photonic Packaging Division
  • ISBN: 0-7918-4277-0 | eISBN: 0-7918-3801-3
  • Copyright © 2007 by ASME

abstract

Board level thermomechanical fatigue lifetimes of five different wafer-level chip scale packages (WCSP’s) with lead-free solder joints were studied by both experiment and finite element method modeling. The effect of three different constitutive laws of the lead-free solder, namely Anand viscoplasticity, power law break-down creep and time hardening creep are also investigated for each of the five packages. The fatigue correlation parameters based on the increment of volume-averaged inelastic strain energy density are deduced for each of the corresponding three constitutive laws. It is demonstrated that the relative error of the predicted lifetime for WCSP with lead-free solder joints can be within 10% compared to experiment. It is found that the fatigue correlation parameters depend strongly on the specific constitutive law. Another important finding is that the fatigue correlation parameters depend on the specific package family. It is also demonstrated that when fatigue correlation parameters calibrated for other package families are applied to WCSPs, the error in predicted lifetimes is consistently large.

Copyright © 2007 by ASME

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