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Thermal Management on Hot Spot Elimination / Junction Temperature Reduction for High Power Density System in Package Structure

[+] Author Affiliations
Chan-Yen Chou, Chung-Jung Wu, Hsiu-Ping Wei, Ming-Chih Yew, Chien-Chia Chiu, Kuo-Ning Chiang

National Tsing Hua University, Hsinchu, Taiwan

Paper No. IPACK2007-33534, pp. 227-232; 6 pages
  • ASME 2007 InterPACK Conference collocated with the ASME/JSME 2007 Thermal Engineering Heat Transfer Summer Conference
  • ASME 2007 InterPACK Conference, Volume 1
  • Vancouver, British Columbia, Canada, July 8–12, 2007
  • Conference Sponsors: Electronic and Photonic Packaging Division
  • ISBN: 0-7918-4277-0 | eISBN: 0-7918-3801-3
  • Copyright © 2007 by ASME


In this paper, a thermal enhanced design for a high power density system in package (SiP) is proposed to resolve the challenge faced by the packaging research community in eliminating the hot spot and reducing the junction temperature in a high operation temperature. The SiP structure includes seven sub-chips which are attached to the chip carrier. The dissipated heat is conducted to the metal slug by thermal vias, while some heat is conducted to the pads by metal traces. Finally, the whole module is connected to the test board by solder paste material. In the thermal enhanced design, a highly conductive material such as solder paste is applied to make an attachment between the chip carrier and the highest power density chip (the power amplifier chip). Besides, some thermal vias are constructed to conduct the dissipated heat from the chip carrier to the metal slug. The new structure greatly improves the thermal performance of the SiP structure. Moreover, the hot spot on the chip carrier is also eliminated in this thermal enhanced SiP structure.

Copyright © 2007 by ASME



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