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Prime Silicon and Silicon-on-Insulator (SOI) Wafer Polishing With Magnetorheological Finishing (MRF)

[+] Author Affiliations
Marc Tricard, Paul R. Dumas, Don Golini, James T. Mooney

QED Technologies, Inc., Rochester, NY

Paper No. IMECE2003-42149, pp. 661-670; 10 pages
doi:10.1115/IMECE2003-42149
From:
  • ASME 2003 International Mechanical Engineering Congress and Exposition
  • Manufacturing
  • Washington, DC, USA, November 15–21, 2003
  • Conference Sponsors: Manufacturing Engineering Division
  • ISBN: 0-7918-3720-3 | eISBN: 0-7918-4663-6, 0-7918-4664-4, 0-7918-4665-2
  • Copyright © 2003 by ASME

abstract

The December 2001 [1, 2] edition of the International Technology Roadmap for Semiconductors [3] (ITRS-2001) identifies several challenges for the manufacturing of silicon and silicon-on-insulator (SOI) wafers. For silicon, edge exclusion, site flatness and nanotopography1 requirements will become extremely challenging. For SOI, requirements for the control of the top silicon layer and its associated uniformity are pushing the limits of metrology. Keeping ± 5% tolerances on thicknesses, gradually decreasing from more than 100nm to less than 20nm for partially depleted devices (let alone from 30 to 3nm for fully depleted devices) is exceeding the capabilities of traditional chemo-mechanical-polishing (CMP) processes [5]. This paper will briefly describe magnetorheological finishing (MRF) and its suitability for prime silicon and SOI wafer polishing. Particular emphasis will be placed on MRF’s ability to improve the global flatness and the total thickness variation (TTV) on prime silicon wafers, and to reduce the nominal thickness of the top silicon layer, while improving thickness uniformity on SOI wafers. The paper will also touch upon the process qualification issues associated with the tight requirements of the semiconductor industry.

Copyright © 2003 by ASME

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