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Characterization of Defects for Effective Gettering in Silicon Wafer and Polysilicon Thin Films

[+] Author Affiliations
Dan O. Macodiyo, Hitoshi Soyama, Kazuo Hayashi

Tohoku University, Sendai, Japan

Paper No. ESDA2006-95340, pp. 963-972; 10 pages
doi:10.1115/ESDA2006-95340
From:
  • ASME 8th Biennial Conference on Engineering Systems Design and Analysis
  • Volume 2: Automotive Systems, Bioengineering and Biomedical Technology, Fluids Engineering, Maintenance Engineering and Non-Destructive Evaluation, and Nanotechnology
  • Torino, Italy, July 4–7, 2006
  • ISBN: 0-7918-4249-5 | eISBN: 0-7918-3779-3
  • Copyright © 2006 by ASME

abstract

The scaling down of commercial products has fueled the rapid development of micro- and nano-electromechanical systems (MEMS/NEMS). The enabling technologies of surface micromachining for silicon has made it compatible with industry strategies towards integrated circuits used in actuation and controls of systems. During the silicon processing, microdefects do occur. If properly controlled, they act as gettering sites for metallic species and hence remove unwanted impurities in the active device regions of semiconductor devices. On the other hand, microdefects can be responsible for plastic deformation of silicon wafer. The occurrence of dislocations in the active device regions causes current leakage and even failure of devices. Determination of the optimum point at which bulk microdefects can be considered to have beneficial gettering effect in silicon wafer and the exact mechanisms by which mobile dislocations are generated in the bulk of an initially dislocation free silicon wafer are not well understood. The purpose of this study is to analyze types of dislocation misfits and the corresponding defect size that is responsible for effective gettering due to cavitation impacts. The authors have already studied electrical characteristics of backside damage gettering by cavitation impact [1–3]. Polysilicon has been grown on thin silicon suboxide layer by a gas-source molecular beam epitaxy (MBE). MBE was done by placing the silicon substrate in an ultra-high vacuum chamber and heating it to 800 °C for 10 min and then at 700 °C for 3 hours at a flow rate of 2.5 sccm. The atomic force microscopy (AFM), micro Raman spectroscopy and transmission electron microscopy (TEM) were used to characterize the Czochralski silicon (CZ–Si) in the plane (100) and poly-Si/SiO2 in the atomic scale before and after gettering the specimen. AFM results showed that the surface roughness and threshold deformation were 2.3 nm and 4.4 nm, respectively. Plan-view TEM analysis of silicon showed the coexistence of single dislocation and narrow dipoles. It can be concluded that cavitation impacts causes dislocation dipoles on CZ-Si(100) which are associated with dislocation loops. The initiation point takes the form of a micro Frank-Read dislocation source, less than 50 nm, that cause dislocation dipoles which are associated with dislocation loops. Plan view TEM observations reveal that the size of the dislocation misfits was approximately 100 nm. The polysilicon surface had a higher residual stresses when it was subjected to cavitation impacts. The cross-sectional TEM observation on poly-Si revealed random crystals on the noncavitated specimens while a mixer of columnar-textured grains on the specimen treated by cavitation. The textured grains have rough edges and the intra-grain size is about 40 nm. Deformation twins and set of streaks from an array of dislocations were observed in the cavitated poly-Si/SiO2 specimens. The spacing between the large grains was 8 nm.

Copyright © 2006 by ASME

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