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A Novel Compact Method for Thermal Modeling of On-Chip Interconnects Based on the Finite Element Method

[+] Author Affiliations
Siva P. Gurrum, Yogendra K. Joshi, William P. King

Georgia Institute of Technology, Atlanta, GA

Koneru Ramakrishna

Motorola, Inc., Austin, TX

Paper No. IMECE2003-41596, pp. 441-445; 5 pages
doi:10.1115/IMECE2003-41596
From:
  • ASME 2003 International Mechanical Engineering Congress and Exposition
  • Electronic and Photonic Packaging, Electrical Systems and Photonic Design, and Nanotechnology
  • Washington, DC, USA, November 15–21, 2003
  • Conference Sponsors: Electronic and Photonic Packaging Division
  • ISBN: 0-7918-3714-9 | eISBN: 0-7918-4663-6, 0-7918-4664-4, 0-7918-4665-2
  • Copyright © 2003 by ASME

abstract

Prediction of the temperature field generated with Joule heating in multilayer interconnect stacks is of critical importance for the design and reliability of future microelectronics. Interconnect failure due to electromigration is strongly dependent on its temperature. Simple models fail to capture thermal interaction between layers and within the layer. Detailed simulations on the other hand, take tremendous time and require large storage. This paper describes a threedimensional compact thermal modeling methodology that captures thermal interactions at a lower computational cost and storage requirements. The method is applicable for arbitrary geometries of interconnects due to the use of the finite element method. Case studies with three interconnects placed on a single level at a pitch of 1.0 μm generating different heat rates are reported. The compact model predicts a temperature rise of 4.11 °C at a current density of 10 MA/cm2 for 6.0 μm long interconnects of 0.18 μm width and an aspect ratio of 2. The error in maximum temperature is about 5% when compared with detailed simulations. The compact model for the current cases consists of 219 nodes whereas the detailed model has 99,000 nodes where temperature is computed.

Copyright © 2003 by ASME

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