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Design of a 0.18um Stable Non-Volatile Boost Circuit in High/Low Temperature Operation

[+] Author Affiliations
Mu-Chun Wang

National Taipei University of Technology, Taipei, Taiwan, R.O.C.; Ming Hsin University of Science & Technology, Hsin-Chu, Taiwan, R.O.C.

Zhen-Ying Hsieh, Shuang-Yuan Chen, Heng-Sheng Huang

National Taipei University of Technology, Taipei, Taiwan, R.O.C.

Chien-Chih Chen

Ming Hsin University of Science & Technology, Hsin-Chu, Taiwan, R.O.C.

Paper No. MNC2007-21083, pp. 305-309; 5 pages
doi:10.1115/MNC2007-21083
From:
  • 2007 First International Conference on Integration and Commercialization of Micro and Nanosystems
  • First International Conference on Integration and Commercialization of Micro and Nanosystems, Parts A and B
  • Sanya, Hainan, China, January 10–13, 2007
  • Conference Sponsors: Nanotechnology Institute
  • ISBN: 0-7918-4265-7 | eISBN: 0-7918-3794-7
  • Copyright © 2007 by ASME

abstract

In this work, we propose the P-MOS diode structure with triple-well process plus MIM capacitors, to establish two non-volatile boosters for flash memory products. Every connecting point in circuits, avoiding the occurrence of dielectric breakdown in gate oxide or p-n junction, was precisely conceived and examined. As the consideration of the system-on-chip (SoC), two stabilized-voltage circuits and two internal ring oscillators were built in. Additionally, to couple the voltage and to stabilize the voltage after several signal-transfer stages, obtaining the output voltage with DC 12V and DC20V, separately, as the input voltage is 3.3V, is necessary. The pumping time, while the high voltage is approached, is only several micro-seconds. The temperature effect with −25 ∼ 75°C range little impacts the booster voltages. The variation, due to temperature contribution, is less than 3%. By the way, this circuit design not only adopts the TSMC 0.18um process design kits, but includes some ESD protection circuits, in output terminals, to provide chip protection. It’s a full and efficient booster design with 0.18um CMOS process. The final dimension of this chip is around 705×978um2 .

Copyright © 2007 by ASME

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