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Three-Mask Fabrication and Optimized Design of First-Level Free-Standing Interconnect for Microelectronics Application

[+] Author Affiliations
Qi Zhu, Lunyu Ma, George Lo, Suresh K. Sitaraman

Georgia Institute of Technology, Atlanta, GA

Paper No. IMECE2003-41833, pp. 171-182; 12 pages
doi:10.1115/IMECE2003-41833
From:
  • ASME 2003 International Mechanical Engineering Congress and Exposition
  • Electronic and Photonic Packaging, Electrical Systems and Photonic Design, and Nanotechnology
  • Washington, DC, USA, November 15–21, 2003
  • Conference Sponsors: Electronic and Photonic Packaging Division
  • ISBN: 0-7918-3714-9 | eISBN: 0-7918-4663-6, 0-7918-4664-4, 0-7918-4665-2
  • Copyright © 2003 by ASME

abstract

Advances in compliant off-chip interconnects have achieved great strides. G-Helix, an electroplated compliant chip-to-substrate interconnect has the potential for accomplishing low-cost, easy-to-fabricate, wafer-level packaging. In this work, the design, fabrication, optimization and reliability of the G-Helix compliant off-chip interconnects have been studied. A three-mask process was used to successfully fabricate the free-standing G-Helix compliant interconnect. The mechanical compliance and the electrical parasitics were studied through numerical and analytical models. Response Surface Methodology (RSM) was used to maximize the mechanical compliance and minimize the electrical parasitics as well as the stresses induced in the interconnect. It is also seen through the models that an array of interconnects will be able to withstand the die and the heat-sink weight without plastically yielding. Also, the G-Helix interconnect assembly on organic printed circuit board using lead-free solder will be able to withstand more than 1000 accelerated thermal cycles without the need for an underfill.

Copyright © 2003 by ASME

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