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Layout Based Full Chip Thermal Simulations of Stacked 3D Integrated Circuits

[+] Author Affiliations
Ashok Raman, Marek Turowski

CFD Research Corporation, Huntsville, AL

Monte Mar

Orora Design Technologies, Inc.

Paper No. IMECE2003-41135, pp. 159-164; 6 pages
doi:10.1115/IMECE2003-41135
From:
  • ASME 2003 International Mechanical Engineering Congress and Exposition
  • Electronic and Photonic Packaging, Electrical Systems and Photonic Design, and Nanotechnology
  • Washington, DC, USA, November 15–21, 2003
  • Conference Sponsors: Electronic and Photonic Packaging Division
  • ISBN: 0-7918-3714-9 | eISBN: 0-7918-4663-6, 0-7918-4664-4, 0-7918-4665-2
  • Copyright © 2003 by ASME

abstract

This paper presents full-chip scale detailed thermal simulations of three-dimensional (3D) integrated circuit (IC) stacks. The inter-layer dielectric (ILD) and inter-metal dielectric (IMD) materials inside 3D IC stacks may cause extensive localized heating. The influence of multiple layers of dielectrics on heat trapping inside the 3D stack is analyzed. Different methods to minimize such localized heating are studied. It is shown that the use of thermal vias is very effective in heat dissipation from the hot spots. Comparisons are made between several 3D IC configurations to verify these conclusions.

Copyright © 2003 by ASME

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