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Three Dimensional Packaging of Bare IC Into Printed Circuit Boards for SIP

[+] Author Affiliations
Erik Jung, Dirk Wojakowski, Alexander Neumann, Rolf Aschenbrenner, Herbert Reichl

Technical University of Berlin, Berlin, Germany

Paper No. IMECE2003-41116, pp. 153-157; 5 pages
doi:10.1115/IMECE2003-41116
From:
  • ASME 2003 International Mechanical Engineering Congress and Exposition
  • Electronic and Photonic Packaging, Electrical Systems and Photonic Design, and Nanotechnology
  • Washington, DC, USA, November 15–21, 2003
  • Conference Sponsors: Electronic and Photonic Packaging Division
  • ISBN: 0-7918-3714-9 | eISBN: 0-7918-4663-6, 0-7918-4664-4, 0-7918-4665-2
  • Copyright © 2003 by ASME

abstract

The demand to miniaturize products especially for mobile applications and autonomous systems is continuing to drive the evolution of electronic products and manufacturing methods. To further the miniaturization of future products the integration of functions on miniaturized subsystems, i.e. System-in-Package (SiP) is a promising approach. Here, use of recent manufacturing methods allows to merge the SiP concept with a volumetric integration of IC’s. Up to now, most of the systems make use of single- or double-sided populated system carriers. A new challenge is to incorporate not only passive components, but as well active circuitry (IC’s) and the necessary thermal management. Ultra thin chips (i.e. silicon dies thinned down to <50μm total thickness) lend themselves to reach these goals. Chips with that thickness can be embedded in the dielectric layers of modern laminate PCB’s. Micro via technology allows to contact the embedded chip to the outer faces of the system circuitry. The aspects of embedding and making the electrical contact as well as the thermal management are highlighted. Results on FEM simulations and technical achievements are presented.

Copyright © 2003 by ASME

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