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Preventing Ceramic Chip Capacitor Cracking During Printing Wiring Board Bending

[+] Author Affiliations
Nathan J. Blattau, Donald B. Barker, Craig D. Hillman

University of Maryland, College Park, MD

Paper No. IMECE2003-42256, pp. 145-152; 8 pages
doi:10.1115/IMECE2003-42256
From:
  • ASME 2003 International Mechanical Engineering Congress and Exposition
  • Electronic and Photonic Packaging, Electrical Systems and Photonic Design, and Nanotechnology
  • Washington, DC, USA, November 15–21, 2003
  • Conference Sponsors: Electronic and Photonic Packaging Division
  • ISBN: 0-7918-3714-9 | eISBN: 0-7918-4663-6, 0-7918-4664-4, 0-7918-4665-2
  • Copyright © 2003 by ASME

abstract

The purpose of this study is to investigate the possibility of using finite element models of varying complexities to better understand and predict the durability of multi-layer ceramic chip capacitors subjected to printed wiring board flexure. This study covers low voltage capacitors (0805, 1206, 1812, 2220 sizes) constructed from X7R ceramic mounted on FR-4 printed wiring boards. Existing failure data obtained from Kemet’s experiments on 0805 and 1206 capacitors is used to establish and verify the failure criterion, which is based upon the tensile stresses in the capacitor. This failure limit is determined by performing a finite element analysis that adequately represents the experiments performed by Kemet. The failure limit (overstress) is then extended to a family of capacitors to predict their durability with regard to printed wiring board flexure. Guidelines can then be established to aid designers in preventing failures of capacitors due to printed wiring board flexure.

Copyright © 2003 by ASME

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