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Using Tolerance-Maps to Generate Frequency Distributions of Clearance for Pin-Hole Assemblies

[+] Author Affiliations
Gaurav Ameta, Joseph K. Davidson, Jami J. Shah

Arizona State University, Tempe, AZ

Paper No. DETC2006-99585, pp. 249-259; 11 pages
doi:10.1115/DETC2006-99585
From:
  • ASME 2006 International Design Engineering Technical Conferences and Computers and Information in Engineering Conference
  • Volume 1: 32nd Design Automation Conference, Parts A and B
  • Philadelphia, Pennsylvania, USA, September 10–13, 2006
  • Conference Sponsors: Design Engineering Division and Computers and Information in Engineering Division
  • ISBN: 0-7918-4255-X | eISBN: 0-7918-3784-X
  • Copyright © 2006 by ASME

abstract

A new mathematical model for representing the geometric variations of lines is extended to include probabilistic representations of 1-D clearance which arise from multidimensional variations of an axis, a hole and a pin-hole assembly. The model is compatible with the ASME/ANSI/ISO Standards for geometric tolerances. Central to the new model is a Tolerance-Map (T-Map), a hypothetical volume of points that models the 3-D variations in location and orientation for a segment of a line (the axis), which can arise from tolerances on size, position, orientation, and form. Here it is extended to model the increase in yield that occurs when maximum material condition (MMC) is specified. The frequency distribution of 1-D clearance is decomposed into manufacturing bias, i.e. toward certain regions of a Tolerance-Map, and into a geometric bias that can be computed from the geometry of multidimensional T-Maps. Although the probabilistic representation in this paper is focused on geometric bias and manufacturing bias is presumed to be uniform, the method is robust enough to include manufacturing bias in the future. Geometric bias alone shows a greater likelihood of small clearances than large clearances between an assembled pin and hole.

Copyright © 2006 by ASME

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