0

Full Content is available to subscribers

Subscribe/Learn More  >

Mechanical and Electrical Study of Linear Spring and J-Spring

[+] Author Affiliations
Lunyu Ma, Qi Zhu, Suresh K. Sitaraman

Georgia Institute of Technology, Atlanta, GA

Paper No. IMECE2002-39683, pp. 387-394; 8 pages
doi:10.1115/IMECE2002-39683
From:
  • ASME 2002 International Mechanical Engineering Congress and Exposition
  • Electronic and Photonic Packaging, Electrical Systems Design and Photonics, and Nanotechnology
  • New Orleans, Louisiana, USA, November 17–22, 2002
  • Conference Sponsors: Electronic and Photonic Packaging Division
  • ISBN: 0-7918-3648-7 | eISBN: 0-7918-1691-5, 0-7918-1692-3, 0-7918-1693-1
  • Copyright © 2002 by ASME

abstract

The integrated circuit (IC) fabrication technology continues to push the limits of microelectronics packaging technologies. Today millions of transistors can be fabricated in a chip of about 1 cm × 1 cm in size, and the required I/O density is about 1600/cm2 . Although tremendous advances have been made in die to substrate interconnect technologies as well as substrate/PWB technologies, these advances have not kept pace with advances in semiconductor technology, and therefore, continue to be a bottleneck for further advances in semiconductor technologies. In addition to fabrication constraints, low cost and reliability are other requirements that affect interconnect development. Wafer-level Packaging (WLP) is an effective solution to address some of these issues. A compliant interconnect, called “J-Spring”, has been proposed and developed at Georgia Institute of Technology. Although based on the same concept of inherent stress-gradient used in the linear spring, the J-Spring will provide greater in-plane compliance. These compliant interconnects can be fabricated in batch at wafer level and the pitch can be as low as 30 μm. The fine pitch can meet and exceed the requirements of International Technology Roadmap for Semiconductor (ITRS) for 2011 [ITRS, 2001] and beyond. J-Springs with different radius, angle, width, and release length have been fabricated on a test wafer. Numerical model has been created to determine the release height based on J-Spring geometry and stress gradients. Also, the compliance of J-Spring has been determined in three orthogonal directions using parametric numerical models. The compliance of J-Spring is compared with the compliance of the linear spring. The proposed compliant interconnects can accommodate the differential displacement due to CTE mismatch between the die and the substrate. In addition, to their mechanical characteristics, their electrical characteristics have been studied as well. The electrical characteristics are dependent on the geometry, dimensions and the materials used.

Copyright © 2002 by ASME
Topics: Springs

Figures

Tables

Interactive Graphics

Video

Country-Specific Mortality and Growth Failure in Infancy and Yound Children and Association With Material Stature

Use interactive graphics and maps to view and sort country-specific infant and early dhildhood mortality and growth failure data and their association with maternal

NOTE:
Citing articles are presented as examples only. In non-demo SCM6 implementation, integration with CrossRef’s "Cited By" API will populate this tab (http://www.crossref.org/citedby.html).

Some tools below are only available to our subscribers or users with an online account.

Related Content

Customize your page view by dragging and repositioning the boxes below.

Related eBook Content
Topic Collections

Sorry! You do not have access to this content. For assistance or to subscribe, please contact us:

  • TELEPHONE: 1-800-843-2763 (Toll-free in the USA)
  • EMAIL: asmedigitalcollection@asme.org
Sign In