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Reliability Evaluation of CSP Using New Flip-Chip Bonding Technology: Both-Sided CSP and Single-Sided CSP

[+] Author Affiliations
Hideo Koguchi, Nipon Taweejun

Nagaoka University of Technology, Nagaoka, Niigata, Japan

Kazuto Nishida, Chie Sasaki

Matushita Electric Industrial Company, Ltd., Osaka, Japan

Paper No. IMECE2002-39682, pp. 379-385; 7 pages
doi:10.1115/IMECE2002-39682
From:
  • ASME 2002 International Mechanical Engineering Congress and Exposition
  • Electronic and Photonic Packaging, Electrical Systems Design and Photonics, and Nanotechnology
  • New Orleans, Louisiana, USA, November 17–22, 2002
  • Conference Sponsors: Electronic and Photonic Packaging Division
  • ISBN: 0-7918-3648-7 | eISBN: 0-7918-1691-5, 0-7918-1692-3, 0-7918-1693-1
  • Copyright © 2002 by ASME

abstract

Chip-size packaging (CSP) attracts largely attentions due to its lighter, thinner and smaller size. In this study, the deformations and the stresses in the CSP fabricated by non-conductive film stud-bump direct interconnection (NSD) were analyzed. The reliability evaluation of single-sided CSP and both-sided CSP were investigated for heat cycles. The material parameters, i.e. stresses, strains and deformations, for achieving a high reliability of CSP were investigated using a finite element method and experiment. The dependency of the life in single-sided CSP and both-sided CSP on the thicknesses of IC and substrate could be expressed using a normal stress in the thickness direction and shear stress in the vertical cross section, respectively.

Copyright © 2002 by ASME

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