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Process-Induced Stress Effect on Reliability of ChipSeal® Passivation Technology

[+] Author Affiliations
Yeong K. Kim, Rudolf Krondorfer, Suresh K. Sitaraman

Georgia Institute of Technology, Atlanta, GA

Paper No. IMECE2002-39681, pp. 369-377; 9 pages
doi:10.1115/IMECE2002-39681
From:
  • ASME 2002 International Mechanical Engineering Congress and Exposition
  • Electronic and Photonic Packaging, Electrical Systems Design and Photonics, and Nanotechnology
  • New Orleans, Louisiana, USA, November 17–22, 2002
  • Conference Sponsors: Electronic and Photonic Packaging Division
  • ISBN: 0-7918-3648-7 | eISBN: 0-7918-1691-5, 0-7918-1692-3, 0-7918-1693-1
  • Copyright © 2002 by ASME

abstract

It is important to take into consideration the process-induced residual stress into reliability prediction modeling. Lack of process-induced stress may lead to error in reliability prediction. Therefore, careful investigation of the stress development is critical. In this paper, the stress development induced by ChipSeal® passivation process technology has been analyzed. The ChipSeal® passivation technology has been developed to enhance the reliability of commercially-off-the-shelf plastic encaptulated microelectronics component by sealing integrated circuit at the wafer level. The analysis takes every process step into account to investigate the temperature effect on the final residual stress. The section of the fabricated structure has been modeled in two different configurations. The stress developments have been simulated by numerical method, and the results have been analyzed to identify the critical location. Three different lengths of metal layer have been considered to investigate the effect of metal layer length structure. Finally, a response surface method is employed to determine the thickness effect of individual layers and to develop design guidelines to enhance ChipSeal® reliability.

Copyright © 2002 by ASME
Topics: Reliability , Stress

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