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Failure Prediction of Flip Chip Packages Using Finite Element Technique

[+] Author Affiliations
Abm Hasan, H. Mahfuz, M. Saha, S. Jeelani

Tuskegee University, Tuskegee, AL

Paper No. IMECE2002-39675, pp. 319-328; 10 pages
  • ASME 2002 International Mechanical Engineering Congress and Exposition
  • Electronic and Photonic Packaging, Electrical Systems Design and Photonics, and Nanotechnology
  • New Orleans, Louisiana, USA, November 17–22, 2002
  • Conference Sponsors: Electronic and Photonic Packaging Division
  • ISBN: 0-7918-3648-7 | eISBN: 0-7918-1691-5, 0-7918-1692-3, 0-7918-1693-1
  • Copyright © 2002 by ASME


Flip-chip electronic package undergoes thermal loading during its curing process and operational life. Due to the thermal expansion coefficient (CTE) mismatch of various components, the flip-chip assembly experiences various types of thermally induced stresses and strains. Experimental measurement of these stresses and strains is extremely tedious and rigorous due to the physical limitations in the dimensions of the flip-chip assembly. While experiments provide accurate assessment of stresses and strains at certain locations, a parallel finite element (FE) analysis and analytical study can complementarily determine the displacement, strain and stress fields over the entire region of the flip-chip assembly. Such combination of experimental, finite element and analytical studies are ideal to yield a successful stress analysis of the flip-chip assembly under the various loading conditions. In this study, a two-dimensional finite element model of the flip-chip consisting of the silicon chip, underfill, solder ball, copper pad, solder mask and substrate has been developed. Various stress components under thermal loading condition ranging from −40°C to 150°C have been determined using both the finite element and analytical methods. Stresses such as (σ11 , σ12 , ε12 etc. are extracted and analyzed for the individual components as well as the entire assembly, and the weakest positions of the flip-chip have been discovered. Detailed description of FE modeling is presented and the different failure modes of chip assembly are discussed.

Copyright © 2002 by ASME



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