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Thermal Stress Induced Void Formation in Semiconductor Interconnect

[+] Author Affiliations
Xiaoling He

Bell Labs, Lucent Technologies, Orlando, FL

Clemens Burda

Case Western Reserve University, Cleveland, OH

Paper No. IMECE2002-39513, pp. 255-258; 4 pages
doi:10.1115/IMECE2002-39513
From:
  • ASME 2002 International Mechanical Engineering Congress and Exposition
  • Electronic and Photonic Packaging, Electrical Systems Design and Photonics, and Nanotechnology
  • New Orleans, Louisiana, USA, November 17–22, 2002
  • Conference Sponsors: Electronic and Photonic Packaging Division
  • ISBN: 0-7918-3648-7 | eISBN: 0-7918-1691-5, 0-7918-1692-3, 0-7918-1693-1
  • Copyright © 2002 by ASME

abstract

Stress voiding is a common defect of the semiconductor interconnect. In thermal cycles, other defects such as the hillocks, delamination can also occur. For the Cu/low-k interconnect, simulation with Ansys is made to analysis the interconnect stress-strain distribution and deformation. Results indicate that stress induced void is prone to form in the via than in the metal lines. Flower defect appear at the via top can also be analyzed based on the stress distribution. It is found that Von-Mises stress represent the localization of the stress concentration, which cause delamination and over-stress failure at the interface of the different materials.

Copyright © 2002 by ASME

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