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Analytic Characterization of Area Array Interconnect Shear Force Behavior

[+] Author Affiliations
Donald B. Barker, Brent M. Mager, Michael D. Osterman

University of Maryland, College Park, MD

Paper No. IMECE2002-39494, pp. 187-194; 8 pages
doi:10.1115/IMECE2002-39494
From:
  • ASME 2002 International Mechanical Engineering Congress and Exposition
  • Electronic and Photonic Packaging, Electrical Systems Design and Photonics, and Nanotechnology
  • New Orleans, Louisiana, USA, November 17–22, 2002
  • Conference Sponsors: Electronic and Photonic Packaging Division
  • ISBN: 0-7918-3648-7 | eISBN: 0-7918-1691-5, 0-7918-1692-3, 0-7918-1693-1
  • Copyright © 2002 by ASME

abstract

Shear forces in the interconnects of electronic devices can cause electrical opens, which result in device failure. The shear forces are often caused by the thermal expansion (CTE) mismatch between a component and the printed wiring board (PWB). In this paper, an elastic strength of materials analytic model, which is demonstrated by Vandevelde [21], is used to characterize the interconnect shear force behavior in area array packages. The benefit of modeling the shear forces is that they can be related to the device life, a relationship obtained by converting shear to average stress, which can be converted to strain and used as input in a failure model equation. The most significant characterization that will be presented is that the maximum shear force behavior in the outermost interconnects can be characterized by three distinct regions of maximum shear force behavior.

Copyright © 2002 by ASME

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