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An Integrated Wafer-Scale Packaging Process for MEMS

[+] Author Affiliations
Thomas W. Kenny, Rob N. Candler, Huimou J. Li, Woo-Tae Park, Junghwa Cho, Holden Li

Stanford University, Stanford, CA

Aaron Partridge, Gary Yama, Marcus Lutz

Robert Bosch Corporation, Palo Alto, CA

Paper No. IMECE2002-39270, pp. 51-54; 4 pages
doi:10.1115/IMECE2002-39270
From:
  • ASME 2002 International Mechanical Engineering Congress and Exposition
  • Electronic and Photonic Packaging, Electrical Systems Design and Photonics, and Nanotechnology
  • New Orleans, Louisiana, USA, November 17–22, 2002
  • Conference Sponsors: Electronic and Photonic Packaging Division
  • ISBN: 0-7918-3648-7 | eISBN: 0-7918-1691-5, 0-7918-1692-3, 0-7918-1693-1
  • Copyright © 2002 by ASME

abstract

Packaging is well known to impose significant cost, performance and fabrication constraints on MEMS devices. We have developed a wafer-scale, integrated packaging process which enables a released MEMS device to be sealed within a thick layer of epi-polysilicon. This encapsulation may be tailored to withstand conventional dicing saws, pick/place chip handling equipment, and even high-pressure injection molding for plastic DIP packages. This architecture can be adapted to a variety of MEMS devices, and is compatible with integrated electronics. This paper will describe this packaging technique and discuss applications.

Copyright © 2002 by ASME

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