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Fine Grinding of Silicon Wafers: Grinding Marks

[+] Author Affiliations
Z. J. Pei

Kansas State University, Manhattan, KS

Alan Strasbaugh

Strasbaugh, Inc., San Luis Obispo, CA

Paper No. IMECE2002-33458, pp. 311-320; 10 pages
doi:10.1115/IMECE2002-33458
From:
  • ASME 2002 International Mechanical Engineering Congress and Exposition
  • Microelectromechanical Systems
  • New Orleans, Louisiana, USA, November 17–22, 2002
  • Conference Sponsors: Microelectromechanical Systems
  • ISBN: 0-7918-3642-8 | eISBN: 0-7918-1691-5, 0-7918-1692-3, 0-7918-1693-1
  • Copyright © 2002 by ASME

abstract

In order to ensure high quality chips with high yield, the base material, semiconductor wafers (over 90% are silicon), must have superior quality. It is critically important to develop new manufacturing processes that allow silicon wafer manufacturers to produce high quality wafers at a reasonably low cost. A newly patented technology—fine grinding of etched silicon wafers—has great potential to manufacture very flat silicon wafers more cost-effectively. This paper presents an investigation of grinding marks in fine grinding. The investigation covers (1) nature of grinding marks, (2) factors that have effects on grinding marks, and (3) approaches to reduce grinding marks. Varying chuck speed during grinding operation is shown to be a very effective approach to reduce grinding marks. Conclusions from this study have direct impacts to the silicon wafer industry.

Copyright © 2002 by ASME

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