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An Yield Model for Electronics Assembly

[+] Author Affiliations
N. Gnanasambandam

Pennsylvania State University

M. Munikrishnan, V. Poyyapakkam, K. Srihari

State University of New York at Binghamton

P. Borgesen

Universal Instruments Corporation

Paper No. IMECE2005-82623, pp. 375-380; 6 pages
doi:10.1115/IMECE2005-82623
From:
  • ASME 2005 International Mechanical Engineering Congress and Exposition
  • Electronic and Photonic Packaging, Electrical Systems Design and Photonics, and Nanotechnology
  • Orlando, Florida, USA, November 5 – 11, 2005
  • Conference Sponsors: Electronic and Photonic Packaging Division
  • ISBN: 0-7918-4217-7 | eISBN: 0-7918-3769-6
  • Copyright © 2005 by ASME

abstract

Managing assembly yield in the Printed Circuit Board (PCB) assembly process is crucial in reducing the overall manufacturing cost of a product. Being faced with electronic components that have high interconnect (pin or solder bump) count, density, and complexity, it is extremely important to streamline the manufacturing losses arising from misplaced or poorly assembled components. In order to achieve this goal, yield models are utilized to anticipate and evaluate problems and their causes. This activity could be potentially implemented at the design stage or at least much before the product reaches the manufacturing floor. This research examines some important factors that affect area array (BGA, CSP, flip chip) assembly yields, taking a two-pronged approach to modeling. Achievable yield is classified into placement and assembly components and is estimated using a simulation model.

Copyright © 2005 by ASME

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