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Stress Analysis of a Novel MEMS Microphone Chip Using Finite Element Analysis

[+] Author Affiliations
Jia Gao, Ronald N. Miles, Weili Cui

State University of New York at Binghamton

Paper No. IMECE2005-82823, pp. 259-267; 9 pages
  • ASME 2005 International Mechanical Engineering Congress and Exposition
  • Electronic and Photonic Packaging, Electrical Systems Design and Photonics, and Nanotechnology
  • Orlando, Florida, USA, November 5 – 11, 2005
  • Conference Sponsors: Electronic and Photonic Packaging Division
  • ISBN: 0-7918-4217-7 | eISBN: 0-7918-3769-6
  • Copyright © 2005 by ASME


Residual stress produces major challenges in the fabrication of MEMS devices. This is particularly true in the development of MEMS microphones since the response of the thin sound-sensitive diaphragm is strongly affected by stress. It is important to predict the effects of fabrication stress on the microphone chip and identify the failure modes to ensure a satisfactory fabrication yield. In this study, a finite element model of the microphone chip is developed to analyze the laminated structure under different fabrication stresses. The model of the microphone chip includes the diaphragm, backplate and sacrificial oxide layers on top of the silicon substrate. Fabrication stresses are included through the use of an equivalent thermal stress. The stresses in the different layers have been estimated based on measurements performed on fabricated test structures. The estimated stresses are simulated in the finite element model. An important factor in determining the process reliability is the compressive stress of the low temperature sacrificial oxide layer (LTO). A variety of stress combinations between different layers with the low temperature oxide layer are investigated. It is found that an adequate level of tensile stress in the backplate is crucial to ensure the fabrication yield. In the designs considered here, silicon nitride in combination with a thin conductive layer is identified as a favorable material for the backplate considering its high modulus and tensile stress in ‘as deposited’ film. In addition, the presence of a LTO layer on the backside of the wafer turns out to be very helpful in reducing the deflection of the unreleased chip and the stress in the diaphragm. In the case where there is a net compressive stress in the laminate, the failure mode is identified by nonlinear analysis. This analysis provides a guideline to select robust materials and tune the fabrication process to ensure a satisfactory fabrication yield.

Copyright © 2005 by ASME



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