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The Characterization of Underfill-Passivation Interface Under Monotonic and Fatigue Loading and Its Application to Flip Chip Reliability Prediction

[+] Author Affiliations
Saketh Mahalingam, Suresh K. Sitaraman

Georgia Institute of Technology

Sandeep Tonapi

General Electric Company

Paper No. IMECE2005-83029, pp. 219-224; 6 pages
doi:10.1115/IMECE2005-83029
From:
  • ASME 2005 International Mechanical Engineering Congress and Exposition
  • Electronic and Photonic Packaging, Electrical Systems Design and Photonics, and Nanotechnology
  • Orlando, Florida, USA, November 5 – 11, 2005
  • Conference Sponsors: Electronic and Photonic Packaging Division
  • ISBN: 0-7918-4217-7 | eISBN: 0-7918-3769-6
  • Copyright © 2005 by ASME

abstract

Flip chip packaging technology is an attractive technique to achieve mechanical and electrical interconnection between the silicon chip and the substrate. Solder joint reliability in flip chip on organic board (FCOB) is enhanced by underfill application. The failure of solder joints in a flip chip package is usually associated with underfill delamination, esp. from the chip passivation. In this work, the fracture toughness of this interface is characterized for a novel no-flow underfill material using an innovative residual stress induced decohesion (RSID) test. Numerical modeling of the chip passivation-underfill interface indicates that the delamination will not progress under monotonic loading. However, the progress of delamination occurs under repeated thermal cycling. An empirical Paris law for underfill delamination has been developed and has been applied to predict delamination in actual flip chip packages. A reasonable agreement between the two is shown.

Copyright © 2005 by ASME

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