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Package and Board Level Study for a Thin Small Outline Package (TSOP) Using Compact Components

[+] Author Affiliations
Amit Kulkarni, Dereje Agonafer

University of Texas at Arlington, Arlington, TX

Steven Groothuis, Humayun Kabir, Scott Johnson

Micron Technology Texas, LLC, Allen, TX

Paper No. IPACK2003-35279, pp. 867-873; 7 pages
doi:10.1115/IPACK2003-35279
From:
  • ASME 2003 International Electronic Packaging Technical Conference and Exhibition
  • 2003 International Electronic Packaging Technical Conference and Exhibition, Volume 2
  • Maui, Hawaii, USA, July 6–11, 2003
  • Conference Sponsors: Electronic and Photonic Packaging Division
  • ISBN: 0-7918-3690-8 | eISBN: 0-7918-3674-6
  • Copyright © 2003 by ASME

abstract

A detail model of 54 lead Thin Small Outline Package (TSOP) was created in Flotherm and validated against experimental data for natural convection and forced convection environments. Next, a compact two-resistor (2R) model was created in Flotherm using compact smart parts. Values of junction-to-case and junction-to-board resistances were taken from experiments. Both the detailed model and the compact model were mounted on a 4-layered standard JEDEC board for natural convection in a standard JEDEC enclosure. With a nominal power of 0.75W applied at the junction, the detailed model and the 2R compact model showed a very good agreement. The results also compared well with experimental data. Next, two models were developed; a detailed model and a corresponding equivalent 2R compact model were mounted on a 4-layered standard JEDEC board and simulated for forced convection with an air velocity of 1 m/s. With a nominal power of 0.75 W applied at the junction, maximum junction temperatures were computed and once again showed very good agreement. Experimental data for forced convection indicated that the maximum junction temperature was in good agreement to the compact model. The study was further extended to do a board level analysis where the detailed TSOP models were mounted on a 6-layered standard DIMM board. In the single sided board arrangement nine such compact models were mounted on one side of the board and maximum junction temperature was noted. Then, the detailed models were replaced by compact models and simulated for forced convection with an air velocity of 1 m/s. Good agreement between detailed model and compact model was seen for the board level analysis. Further the compact models were simulated for a double-sided arrangement in which eighteen such compact models were mounted nine on each sided of the board. The assembly was simulated for forced convection with an air velocity of 1 m/s. Nominal power applied at junction for each of the eighteen modules was 0.3 W. Maximum temperature for the double sided arrangement of DIMM board was thus computed.

Copyright © 2003 by ASME

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