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V-PAC: Vertical Packaging for Assembly-Compatible Chip Stacks

[+] Author Affiliations
Vincent Malba, Leland B. Evans, Christopher D. Harvey, Anthony F. Bernhardt

Lawrence Livermore National Laboratory, Livermore, CA

Paper No. IPACK2003-35194, pp. 853-858; 6 pages
doi:10.1115/IPACK2003-35194
From:
  • ASME 2003 International Electronic Packaging Technical Conference and Exhibition
  • 2003 International Electronic Packaging Technical Conference and Exhibition, Volume 2
  • Maui, Hawaii, USA, July 6–11, 2003
  • Conference Sponsors: Electronic and Photonic Packaging Division
  • ISBN: 0-7918-3690-8 | eISBN: 0-7918-3674-6
  • Copyright © 2003 by ASME

abstract

A new process for making high-density memory stacks which are completely compatible with typical electronic assembly techniques is presented. The process uses PECVD-SiO2 passivation, laser direct-writing, electrodeposited photoresist, and metal electroplating to form a reroute pattern extending from the input/output (I/O) pads on top of the chip directly onto the chip sidewalls. With the I/O available for interconnection on the side of the chip, four memory chips are stacked together with one silicon reroute chip. A high-temperature compatible anisotropically conductive adhesive is used to connect a flex circuit to the sidewall I/O pads of the memory chips and the reroute die. The reroute die’s sidewall pads connect to a pattern on the die surface which redistributes the I/O for connection to a leadframe. The lead frame is epoxied to the reroute die, and wirebonded to complete the electrical connection. The leadframe/stack assembly is then encapsulated with an epoxy potting compound, and the leads are formed and trimmed, creating a chip stack which is indistinguishable from a standard IC package.

Copyright © 2003 by ASME

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