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Design Optimization of Off-Chip Inductors

[+] Author Affiliations
Lin Jin, Albert Chee W. Lu, Lai L. Wai, Wei Fan

Singapore Institute of Manufacturing Technology, Singapore

Aik Chong Tan, Kai Chong Chan

Ellipsiz Microfab Technology (S) Pte Ltd., Singapore

Paper No. IPACK2003-35223, pp. 735-739; 5 pages
doi:10.1115/IPACK2003-35223
From:
  • ASME 2003 International Electronic Packaging Technical Conference and Exhibition
  • 2003 International Electronic Packaging Technical Conference and Exhibition, Volume 2
  • Maui, Hawaii, USA, July 6–11, 2003
  • Conference Sponsors: Electronic and Photonic Packaging Division
  • ISBN: 0-7918-3690-8 | eISBN: 0-7918-3674-6
  • Copyright © 2003 by ASME

abstract

A solution space design methodology is presented for optimization of off-chip inductors. The analysis has been performed for an advanced wafer level redistribution manufacturing process. Electromagnetic simulations were performed to extract the characteristics of different inductor designs. It was observed that the design optimization should be tuned to the operating frequency.

Copyright © 2003 by ASME

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