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On the Correlation Between Power Density Distribution and Junction-Case Thermal Resistance for Electronic Packages

[+] Author Affiliations
Sai Ankireddi, Henry H. Jung, James Jones

Sun Microsystems, Inc., Sunnyvale, CA

Paper No. IPACK2003-35310, pp. 665-674; 10 pages
doi:10.1115/IPACK2003-35310
From:
  • ASME 2003 International Electronic Packaging Technical Conference and Exhibition
  • 2003 International Electronic Packaging Technical Conference and Exhibition, Volume 2
  • Maui, Hawaii, USA, July 6–11, 2003
  • Conference Sponsors: Electronic and Photonic Packaging Division
  • ISBN: 0-7918-3690-8 | eISBN: 0-7918-3674-6
  • Copyright © 2003 by ASME

abstract

When comparing two electronic packages identical in all respects except die plan dimensions and power, wherein the package with the smaller die is associated with a lower power, it is often hypothesized that the lower-powered package would have a lower junction-case thermal resistance. This hypothesis is generally based on the questionable argument that because the smaller package has lower power, its internal temperatures should be lower and hence a lower junction-case resistance should be ‘intuitively’ expected. In this article we show that drawing inferences about trends in junction-case resistance based merely on power trends, as outlined above, can be incorrect. In order to address this issue and provide better ‘indicators’ for comparing thermal performance across packages, we introduce the concept of the Power Density Distribution (PDD) and show how it relates with the junction-case thermal resistance. To illustrate its use in comparing thermal performance of packages we consider examples of several ICs with different die size/power combinations. Additionally, we also note the correlation between peaks in the spatial distribution of the power density and those of the die temperature distribution; in effect, this furnishes a simple way to identify candidate hot-spot locations on the die without resorting to extensive numerical thermal simulation/testing. We illustrate this intuitively anticipated concept for a variety of power distribution scenarios in some of our example IC packages.

Copyright © 2003 by ASME

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