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Measurement of Stress and Delamination in Flip Chip on Laminate Assemblies

[+] Author Affiliations
M. Kaysar Rahim, Jeffrey C. Suhling, D. Scott Copeland, Richard C. Jaeger, Pradeep Lall

Auburn University, Auburn, AL

Paper No. IPACK2003-35319, pp. 907-921; 15 pages
doi:10.1115/IPACK2003-35319
From:
  • ASME 2003 International Electronic Packaging Technical Conference and Exhibition
  • 2003 International Electronic Packaging Technical Conference and Exhibition, Volume 1
  • Maui, Hawaii, USA, July 6–11, 2003
  • Conference Sponsors: Electronic and Photonic Packaging Division
  • ISBN: 0-7918-3690-8 | eISBN: 0-7918-3674-6
  • Copyright © 2003 by ASME

abstract

Mechanical stress distributions in packaged silicon die that have resulted during assembly or environmental testing can be accurately characterized using test chips incorporating integral piezoresistive sensors. In this paper, an overview of recent measurements made in flip chip on laminate assemblies with (111) silicon test chips is presented. Transient die stress measurements have been made during underfill cure, and the room temperature die stresses in final cured assemblies have been compared for several different underfill encapsulants. The experimental stress measurements in the flip chip samples were then correlated with finite element predictions for the tested configurations. In addition, stress variations have been monitored in the assembled flip chip die as the test boards were subjected to slow temperature changes from −40 to +150°C. Finally the stress variations occurring during thermal cycling from −40 to +125°C have been characterized. These measurements have been correlated with the delaminations occurring at the die passivation to underfill interface measured using C-mode Scanning Acoustic Microscopy (C-SAM). Using the measurements and numerical simulations, valuable insight has been gained on the effects of assembly variables and underfill material properties on the reliability of flip chip packages.

Copyright © 2003 by ASME

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