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Wafer Scale Encapsulation of MEMS Devices

[+] Author Affiliations
Woo-Tae Park, Rob N. Candler, Huimou J. Li, Junghwa Cho, Holden Li, Thomas W. Kenny

Stanford University, Stanford, CA

Aaron Partridge, Gary Yama, Markus Lutz

Robert Bosch Corporation, Palo Alto, CA

Paper No. IPACK2003-35032, pp. 209-212; 4 pages
doi:10.1115/IPACK2003-35032
From:
  • ASME 2003 International Electronic Packaging Technical Conference and Exhibition
  • 2003 International Electronic Packaging Technical Conference and Exhibition, Volume 1
  • Maui, Hawaii, USA, July 6–11, 2003
  • Conference Sponsors: Electronic and Photonic Packaging Division
  • ISBN: 0-7918-3690-8 | eISBN: 0-7918-3674-6
  • Copyright © 2003 by ASME

abstract

MEMS packaging has always been a field of great importance since it can dominate the cost and size of a final working device. Considering this, we have concentrated on developing a wafer-scale encapsulation scheme which uses a thick epi-poly (epitaxially deposited poly silicon) layer as the sealing layer. This approach allows the use of conventional post processing, such as dicing, wire bonding, and other standard handling and mounting techniques. We also can minimize the chip area used for packaging, in some cases reducing the chip size by ×5 from what was required for silicon fusion bonded covers. This packaging scheme can be used for various MEMS devices and can be integrated with other electronics. This paper will discuss the packaging process and show some preliminary results.

Copyright © 2003 by ASME

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