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Optimization of Bulk Thermoelectric Modules for Chip Cooling Applications

[+] Author Affiliations
Kazuhiko Fukutani, Ali Shakouri

University of California at Santa Cruz, Santa Cruz, CA

Paper No. IPACK2005-73410, pp. 2179-2183; 5 pages
doi:10.1115/IPACK2005-73410
From:
  • ASME 2005 Pacific Rim Technical Conference and Exhibition on Integration and Packaging of MEMS, NEMS, and Electronic Systems collocated with the ASME 2005 Heat Transfer Summer Conference
  • Advances in Electronic Packaging, Parts A, B, and C
  • San Francisco, California, USA, July 17–22, 2005
  • Conference Sponsors: Heat Transfer Division and Electronic and Photonic Packaging Division
  • ISBN: 0-7918-4200-2 | eISBN: 0-7918-3762-9
  • Copyright © 2005 by ASME

abstract

The use of bulk thermoelectric (TE) coolers for thermal management of integrated circuit (IC) chips is analyzed by a detailed electrothermal model. Various ideal and non-ideal parameters that affect the maximum cooling performance are discussed. Thermal resistance between the hot side of the thermoelectric module and ambient is a key parameter determining maximum heat dissipation in the IC chip if its temperature should be kept below a critical value. We show that the thermoelectric geometry factor (the ratio of the leg’s cross sectional area to its length) and the TE module operating current can be optimized to significantly increase the maximum power dissipation. There is an optimum leg thickness that gives the highest cooling power density to the IC chip and further thinning of the TE module will degrade the performance. The optimum thickness and the corresponding maximum cooling power density are calculated. The effect of various material properties are also discussed.

Copyright © 2005 by ASME
Topics: Cooling , Optimization

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