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Thermoelectric Micro-Cooler for Hot-Spot Thermal Management

[+] Author Affiliations
Peng Wang, Avram Bar-Cohen, Bao Yang

University of Maryland, College Park, MD

Gary L. Solbrekken

University of Missouri at Columbia, Columbia, MO

Yan Zhang, Ali Shakouri

University of California at Santa Cruz, Santa Cruz, CA

Paper No. IPACK2005-73244, pp. 2161-2171; 11 pages
  • ASME 2005 Pacific Rim Technical Conference and Exhibition on Integration and Packaging of MEMS, NEMS, and Electronic Systems collocated with the ASME 2005 Heat Transfer Summer Conference
  • Advances in Electronic Packaging, Parts A, B, and C
  • San Francisco, California, USA, July 17–22, 2005
  • Conference Sponsors: Heat Transfer Division and Electronic and Photonic Packaging Division
  • ISBN: 0-7918-4200-2 | eISBN: 0-7918-3762-9
  • Copyright © 2005 by ASME


Driven by shrinking feature sizes, microprocessor “hot-spots” — with their associated high heat flux and sharp temperature gradients — have emerged as the primary “driver” for on-chip thermal management of today’s IC technology. Solid state thermoelectric micro-coolers offer great promise for reducing the severity of on-chip “hot-spots”, but the theoretical cooling potential of these devices, fabricated on the back of the silicon die in an IC package, has yet to be determined. The results of a three-dimensional electro-thermal finite-element modeling study of such a micro-cooler are presented. Attention is focused on the hot-spot temperature reductions associated with variations in micro-cooler geometry, chip thickness, and chip doping concentration, along with the parasitic Joule heating effects from the electrical contact resistance and current flow through the silicon. The modeling results help to define the optimum solid-state cooling configuration and reveal that, for the conditions examined, nearly 80% of the hot-spot temperature rise of 2.5°C can be removed from a 70μm × 70μm, 680W/cm2 hot-spot on a 50μm thick silicon die with a single micro-cooler.

Copyright © 2005 by ASME



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