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Effect of the Device Structure in Electro-Thermal Analysis of Si CMOS

[+] Author Affiliations
Tomoyuki Hatakeyama, Kazuyoshi Fushinobu, Ken Okazaki

Tokyo Institute of Technology, Tokyo, Japan

Paper No. IPACK2005-73151, pp. 2073-2078; 6 pages
doi:10.1115/IPACK2005-73151
From:
  • ASME 2005 Pacific Rim Technical Conference and Exhibition on Integration and Packaging of MEMS, NEMS, and Electronic Systems collocated with the ASME 2005 Heat Transfer Summer Conference
  • Advances in Electronic Packaging, Parts A, B, and C
  • San Francisco, California, USA, July 17–22, 2005
  • Conference Sponsors: Heat Transfer Division and Electronic and Photonic Packaging Division
  • ISBN: 0-7918-4200-2 | eISBN: 0-7918-3762-9
  • Copyright © 2005 by ASME

abstract

Numerical calculation of submicron silicon MOSFET and CMOS device is performed. In order to have a higher degree of integration, the distance between two MOSFETs in CMOS structure can be decreased. But decreasing the distance between two MOSFETs results in an electrical interaction. In this research, by comparing the calculation result of n-type and p-type MOSFET and that of CMOS, we examine the interaction mechanism between n-type and p-type MOSFET in CMOS device when the distance between n-type and p-type MOSFET is decreased. From the calculated results, we investigate that the reason of the interaction between two MOSFET in CMOS is the forward bias at the p-n junction of substrate. Furthermore, we can estimate the distance, at the case of interaction, from the results of n-type and p-type MOSFET separately model, not from the results of CMOS model.

Copyright © 2005 by ASME

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