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The Characterization of Damage Propagation in BGA’s on Flip-Chip Electronic Packages

[+] Author Affiliations
Kayleen L. E. Helms, Betty Phillips

Intel Corporation, Chandler, AZ

Paper No. IPACK2005-73429, pp. 1565-1573; 9 pages
doi:10.1115/IPACK2005-73429
From:
  • ASME 2005 Pacific Rim Technical Conference and Exhibition on Integration and Packaging of MEMS, NEMS, and Electronic Systems collocated with the ASME 2005 Heat Transfer Summer Conference
  • Advances in Electronic Packaging, Parts A, B, and C
  • San Francisco, California, USA, July 17–22, 2005
  • Conference Sponsors: Heat Transfer Division and Electronic and Photonic Packaging Division
  • ISBN: 0-7918-4200-2 | eISBN: 0-7918-3762-9
  • Copyright © 2005 by ASME

abstract

A characterization study is undertaken to monitor damage progression at the second-level interconnect in BGA’s on flip-chip electronic packages. Specifically, the progression of solder joint cracking under use conditions (thermal and combined thermomechanical loading) is investigated. The study uses a multi-color dye and peel failure analysis technique to track the initiation and propagation of solder joint cracks under loading. The approach being used differs from conventional failure analysis techniques in that multiple measurements of damage growth are obtained from the same part providing a full damage history. By using multiple dye colors, all crack initiation points, directions of propagation, and surface crack areas are obtainable experimentally. The scope of the study includes investigating the impact of such factors as die size, package size, BGA size, BGA pitch, enabling load, and internal heat spreaders (IHS’s) on the damage history observed. Based on this study, investigation of sequential loading can be pursued to identify directions and design guidelines for improving solder joint reliability of future BGA’s on flip-chip electronic packages.

Copyright © 2005 by ASME

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