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Solder Joint Reliability Prediction of Flip Chip Packages Under Shock Loading Environment

[+] Author Affiliations
Wei Keat Loh

Intel Technology Penang, Penang, Malaysia

Luke J. Garner

Intel Corporation, Chandler, AZ

Paper No. IPACK2005-73213, pp. 1433-1440; 8 pages
doi:10.1115/IPACK2005-73213
From:
  • ASME 2005 Pacific Rim Technical Conference and Exhibition on Integration and Packaging of MEMS, NEMS, and Electronic Systems collocated with the ASME 2005 Heat Transfer Summer Conference
  • Advances in Electronic Packaging, Parts A, B, and C
  • San Francisco, California, USA, July 17–22, 2005
  • Conference Sponsors: Heat Transfer Division and Electronic and Photonic Packaging Division
  • ISBN: 0-7918-4200-2 | eISBN: 0-7918-3762-9
  • Copyright © 2005 by ASME

abstract

Solder joint reliability under shock loading condition has been a concern over the years especially with constant reductions in the characteristic dimensions of the package and the solder joint. With the impeding transition to lead free solder, attention has moved from temperature cycle failure to mechanical shock failure. A method has been developed that employs a specially designed shock test board (STB) to characterize the solder joint performance as a function of board surface strain. This unique test board can be adapted to a wide range of test and boundary conditions. Using this board, a range of shock inputs is tested to establish correlation of the dynamic response and solder joint damage severity. The effects of package size, board thickness, and solder ball pitch are included in this paper to highlight the critical design factors for solder joint reliability in shock. This method can be used to characterize solder joint performance at the component level, early in development. One can also provide board strain based design limits guide system design and prevent late discovery of solder joint issues. Modal analysis based finite element models have been used to supplement understanding of the board response. The model demonstrates good correlation of the strain on the board and the stresses developed in the solder joint. The modeling data also suggested that the maximum principal stress at the solder joint face is a good failure criterion as it maps well with the actual failure locus found.

Copyright © 2005 by ASME

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