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Modeling of Thermo-Mechanical Stresses in Copper Interconnect/Low-k Dielectric Systems

[+] Author Affiliations
Y.-L. Shen

University of New Mexico, Albuquerque, NM

Paper No. IPACK2005-73450, pp. 1323-1330; 8 pages
  • ASME 2005 Pacific Rim Technical Conference and Exhibition on Integration and Packaging of MEMS, NEMS, and Electronic Systems collocated with the ASME 2005 Heat Transfer Summer Conference
  • Advances in Electronic Packaging, Parts A, B, and C
  • San Francisco, California, USA, July 17–22, 2005
  • Conference Sponsors: Heat Transfer Division and Electronic and Photonic Packaging Division
  • ISBN: 0-7918-4200-2 | eISBN: 0-7918-3762-9
  • Copyright © 2005 by ASME


Systematic finite element analyses are carried out to model the thermomechanical stresses in on-chip copper interconnect systems. Constitutive behavior of encapsulated copper films, determined by experimentally measuring the stress-temperature response during thermal cycling, is used in the model for predicting stresses in copper interconnect/low-k dielectric structures. Various combinations of oxide and polymer-based low-k dielectric schemes are considered. The evolution of stresses and deformation pattern in the dual-damascene copper, barrier layers, and the dielectrics is seen to have direct connections to the structural integrity of contemporary and future-generation devices. In particular, stresses experienced by the thin barrier layers and the mechanically weak low-k dielectrics are critically assessed. A parametric analysis on the influence of low-k material properties is also conducted. Practical implications in reliability issues such as voiding, interface fracture, electromigration and dielectric failure are discussed.

Copyright © 2005 by ASME
Topics: Copper , Stress , Modeling



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