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Measurement of Electronic Packaging Material Behavior and Flip Chip Die Stresses at Extreme Low Temperatures

[+] Author Affiliations
M. Kaysar Rahim, Jeffrey C. Suhling, Richard C. Jaeger, M. Saiful Islam, Hongtao Ma, Chang Lin, Pradeep Lall, Roy Knight

Auburn University, Auburn, AL

Mark Strickland, Jim Blanche

NASA Marshall Space Flight Center, Marshall Space Flight Center, AL

Paper No. IPACK2005-73349, pp. 1253-1262; 10 pages
doi:10.1115/IPACK2005-73349
From:
  • ASME 2005 Pacific Rim Technical Conference and Exhibition on Integration and Packaging of MEMS, NEMS, and Electronic Systems collocated with the ASME 2005 Heat Transfer Summer Conference
  • Advances in Electronic Packaging, Parts A, B, and C
  • San Francisco, California, USA, July 17–22, 2005
  • Conference Sponsors: Heat Transfer Division and Electronic and Photonic Packaging Division
  • ISBN: 0-7918-4200-2 | eISBN: 0-7918-3762-9
  • Copyright © 2005 by ASME

abstract

High stresses in semiconductor die and other packaging elements can be developed in electronic assemblies subjected to extremely low ambient temperatures leading to reliability concerns. In this work, we have characterized and modeled the silicon die stresses occurring in flip chip assemblies at low temperatures. Stress measurements have been made at temperatures down to −180°C using test chips incorporating piezoresistive sensor rosettes. The obtained stress measurement data have been correlated with the predictions of nonlinear finite element models. A microtester has been used to characterize the stress-strain behavior of the solders and encapsulants from −180 to +150°C to aid in this modeling effort.

Copyright © 2005 by ASME

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