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Ceramic Via Wafer-Level Packaging for MEMS

[+] Author Affiliations
John M. Heck, Leonel R. Arana, Bill Read, Thomas S. Dory

Intel Corporation, Santa Clara, CA

Paper No. IPACK2005-73369, pp. 1069-1074; 6 pages
  • ASME 2005 Pacific Rim Technical Conference and Exhibition on Integration and Packaging of MEMS, NEMS, and Electronic Systems collocated with the ASME 2005 Heat Transfer Summer Conference
  • Advances in Electronic Packaging, Parts A, B, and C
  • San Francisco, California, USA, July 17–22, 2005
  • Conference Sponsors: Heat Transfer Division and Electronic and Photonic Packaging Division
  • ISBN: 0-7918-4200-2 | eISBN: 0-7918-3762-9
  • Copyright © 2005 by ASME


We will present a novel approach to wafer level packaging for micro-electro-mechanical systems. Like most common MEMS packaging methods today, our approach utilizes a wafer bonding process between a cap wafer and a MEMS device wafer. However, unlike the common methods that use a silicon or glass cap wafer, our approach uses a ceramic wafer with built-in metal-filled vias, that has the same size and shape as a standard 150 mm silicon wafer. This ceramic via wafer packaging method is much less complex than existing methods, since it provides hermetic encapsulation and electrical interconnection of the MEMS devices, as well as a solderable interface on the outside of the package for board-level interconnection. We have demonstrated successful ceramic via wafer-level packaging of MEMS switches using eutectic gold-tin solder as well as tin-silver-copper solder combined with gold thermo-compression bonding. In this paper, we will present the ceramic via MEMS package architecture and discuss the associated bonding and assembly processes.

Copyright © 2005 by ASME



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