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On Measurement of Effective Silicon Backend Strength Using Bump Pull/Shear Techniques

[+] Author Affiliations
Sandeep Sane, Shalabh Tandon, Biju Chandran, Tsgereda Alazar, Leonard R. Sorenson

Intel Corporation, Chandler, AZ

Paper No. IPACK2005-73306, pp. 965-969; 5 pages
  • ASME 2005 Pacific Rim Technical Conference and Exhibition on Integration and Packaging of MEMS, NEMS, and Electronic Systems collocated with the ASME 2005 Heat Transfer Summer Conference
  • Advances in Electronic Packaging, Parts A, B, and C
  • San Francisco, California, USA, July 17–22, 2005
  • Conference Sponsors: Heat Transfer Division and Electronic and Photonic Packaging Division
  • ISBN: 0-7918-4200-2 | eISBN: 0-7918-3762-9
  • Copyright © 2005 by ASME


Integrating a low-K ILD layer within silicon is key to reducing RC delays. However, low-K ILD materials typically have low mechanical strength, making their incorporation with lead free interconnects an industry-wide challenge. It is well known that conversion to lead free first level interconnects increases die backend stresses due to the higher melting temperature and increased solder stiffness. The paper will focus on the measurement of the effective silicon backend strength after subjecting the dice to different fabrication and assembly steps. The effective strength will also be evaluated post reliability stress exposure to eventually understand the life of these films. The paper will describe how a commercially available Dage 4000 tool was modified for this application. Bump pull was carried out using a 100μm tweezers, while bump shear used 1mil (25.4μm) wide stylus. Static and dynamic calibration was first carried out to ensure repeatability and reproducibility of the results. Peak force and failure modes were used as metrics to compare the effectiveness of different experimental legs. Traditional failure analysis approach of mechanical polishing, or when needed, use of FIB for sample preparation, with subsequent SEM/EDX analysis was utilized to understand the failure mechanism. Data suggests that shear and pull lead to different failure modes. Bump shear mainly led to failure at the bump/polyimide interface and did not necessarily correspond to the weakest layer or interface in the silicon backend. Whereas bump-pull, which applies tensile force to the stack up, lead to failures in the weakest layer, typically the low-K ILD, in the silicon backend. Hence, bump pull provided the advantage over shear as it allowed evaluation of the weakest interface in the stack up. Two case studies are discussed to demonstrate on how bump pull/shear metrologies were used to understand the impact of different assembly/FAB process variables and highly accelerated steam test (HAST) reliability stress on silicon backend strength. First case study shows influence of assembly flux on silicon backend strength, while second case study describes impact of HAST on different FAB backend processes.

Copyright © 2005 by ASME



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