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Wafer Level Package Challenges: Fabrication Methodology, Packaging Infrastructure and Die-Shrink Considerations

[+] Author Affiliations
Vern Solberg

Tessera, San Jose, CA

Paper No. IPACK2005-73253, pp. 921-925; 5 pages
doi:10.1115/IPACK2005-73253
From:
  • ASME 2005 Pacific Rim Technical Conference and Exhibition on Integration and Packaging of MEMS, NEMS, and Electronic Systems collocated with the ASME 2005 Heat Transfer Summer Conference
  • Advances in Electronic Packaging, Parts A, B, and C
  • San Francisco, California, USA, July 17–22, 2005
  • Conference Sponsors: Heat Transfer Division and Electronic and Photonic Packaging Division
  • ISBN: 0-7918-4200-2 | eISBN: 0-7918-3762-9
  • Copyright © 2005 by ASME

abstract

Although the concept of wafer level packaging (“WLP”) is not new, the industry has yet to widely adopt WLP for volume manufacturing. Before the industry can do so, it must first overcome several challenges. The following are considered to be of primary concern: 1. High volume WLP fabrication methodology must become widely available. While several companies have demonstrated redistribution techniques that could prove practical for volume manufacturing of WLP, most of these techniques are proprietary and not available for wide adoption. 2. WLP manufacturers must leverage the existing assembly infrastructure as much as possible. Otherwise, WLP manufacturers will not be able to keep costs down. Unfortunately, with respect to testing and handling, the existing infrastructure will likely have to be extended. 3. WLP poses the new problem of designing a die-sized package with a footprint that remains constant despite die-shrink and other changes that are likely to occur from one generation of a die to the next. During the planning phase of the product developers must maintain two significant features: the contact size and pitch selected for the wafer level packaged IC must remain consistent from one die generation to the other, and the array pattern must accommodate efficient conductor routing on the circuit board. In this paper, the author will discuss these issues and explore a wafer level package methodologies, that addresses key aspects of the existing package assembly infrastructure that could be leveraged or extended, and the criteria for defining a practical contact array pattern with consideration of die shrink projections.

Copyright © 2005 by ASME

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