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Thermal Management for Chip-Scale Atomic Clocks

[+] Author Affiliations
Alexander Laws, Richard Y. J. Chang, Victor M. Bright, Y. C. Lee

University of Colorado, Boulder, CO

Paper No. IPACK2005-73444, pp. 741-745; 5 pages
  • ASME 2005 Pacific Rim Technical Conference and Exhibition on Integration and Packaging of MEMS, NEMS, and Electronic Systems collocated with the ASME 2005 Heat Transfer Summer Conference
  • Advances in Electronic Packaging, Parts A, B, and C
  • San Francisco, California, USA, July 17–22, 2005
  • Conference Sponsors: Heat Transfer Division and Electronic and Photonic Packaging Division
  • ISBN: 0-7918-4200-2 | eISBN: 0-7918-3762-9
  • Copyright © 2005 by ASME


Power dissipation of chip-scale atomic clocks is one of the major design considerations. The largest power dissipation is for temperature control of the vertical-cavity surface-emitting laser (VCSEL) and cesium vapor cell. For example, the temperature of the VCSEL and Cs cell have to both be at 70±0.1°C or there will be frequency shift which will ruin the lock of the clock. These temperatures have to be maintained even under a large temperature variation such as −40°C to 50°C. There are three major thermal designs to consider: a) micro-heaters to fine-tune the temperatures of VCSEL and Cs cell, b) use of waste heat from other units to heat the system when outside temperature is low, and c) use of a thermal switch to release any extra waste heat when ambient temperatures are high. These three thermal designs have been incorporated in to a thermal test vehicle, which will be used to develop a thermal management design for the clock. This paper describes the proposed clock design, creation of the thermal test vehicle and development of a bimetallic snap based thermal conduction switch. The switch has been demonstrated to change thermal resistance from 52.9±2.8 K/W when the switch is open to 19.5±1.1 K/W with the switch closed.

Copyright © 2005 by ASME



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