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The Effect of Die Attach Voiding on the Thermal Resistance of Chip Level Packages

[+] Author Affiliations
Amy S. Fleischer, Barry C. Johnson

Villanova University, Villanova, PA

Li-Hsin Chang

University of Arizona, Tucson, AZ

Paper No. IPACK2005-73224, pp. 299-304; 6 pages
doi:10.1115/IPACK2005-73224
From:
  • ASME 2005 Pacific Rim Technical Conference and Exhibition on Integration and Packaging of MEMS, NEMS, and Electronic Systems collocated with the ASME 2005 Heat Transfer Summer Conference
  • Advances in Electronic Packaging, Parts A, B, and C
  • San Francisco, California, USA, July 17–22, 2005
  • Conference Sponsors: Heat Transfer Division and Electronic and Photonic Packaging Division
  • ISBN: 0-7918-4200-2 | eISBN: 0-7918-3762-9
  • Copyright © 2005 by ASME

abstract

During semiconductor manufacturing, voids are easily formed in the die attach bond layer and are found to form, grow and coalesce with thermal cycling. The presence of such voids is known to adversely affect the package thermal resistance, but to this point, not enough data exists to precisely analyze the effects of void size, configuration and depth. Using an innovative experimental method the present study investigates these effects with a carefully controlled void geometry. The results show that the thermal resistance increases linearly with void percentage for random voids, but increases exponentially for contiguous voids.

Copyright © 2005 by ASME

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