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Circuit-Thermal Collaboration Design Method for Outline Design Stage of Mobile Terminal

[+] Author Affiliations
Yoshiharu Iwata, Shintaro Hayashi, Ryohei Satoh, Kozo Fujimoto

Osaka University, Osaka, Japan

Paper No. IPACK2005-73157, pp. 225-231; 7 pages
  • ASME 2005 Pacific Rim Technical Conference and Exhibition on Integration and Packaging of MEMS, NEMS, and Electronic Systems collocated with the ASME 2005 Heat Transfer Summer Conference
  • Advances in Electronic Packaging, Parts A, B, and C
  • San Francisco, California, USA, July 17–22, 2005
  • Conference Sponsors: Heat Transfer Division and Electronic and Photonic Packaging Division
  • ISBN: 0-7918-4200-2 | eISBN: 0-7918-3762-9
  • Copyright © 2005 by ASME


The device layout design on the circuit board has a common method of performing a thermal design after the circuit design that is the main performance. But, there is no remaining budget of thermal design of the high performance mobile terminal. Then, a large feedback loop of the design from thermal detail design to outline design is occurred on high performance mobile terminal design. For this purpose, we build upon the high-speed module-based thermal analysis. But the design time is very long with using the general optimization method, i.e., GA, SA. Then, we need more high-speed design method. For this purpose, we have proposed the modularized high-speed layered thermal design method based on the boundary conditions between modules. In this report, we constructed the high-speed circuit-thermal collaboration design method at the outline design stage. This design method is collaborated at decision of boundary conditions between both circuit-thermal design methods. Furthermore, this design method, which computes the Pareto solutions set by changing the weight of each design performance index, was constructed. Moreover, we performed a layout design of a board with four devices mounted on top of the circuit board as a case study. The collaboration design solution between thermal layout design (total temperature rise of device =>min.) and circuit layout design (total circuit line length => min.) was computed in about 250sec, and the Pareto solutions set were computed in about 5000sec.

Copyright © 2005 by ASME



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