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System Level Considerations in the Incorporation of a Component Thermal Model for an Automotive Application

[+] Author Affiliations
Victor Chiriac, Tom Lee

Freescale Semiconductor, Inc., Tempe, AZ

Arvind Krishna, Venkata Krishnan, Rodney Lawrence

Delphi Delco Electronics Systems, Kokomo, IN

Paper No. IPACK2005-73101, pp. 119-127; 9 pages
doi:10.1115/IPACK2005-73101
From:
  • ASME 2005 Pacific Rim Technical Conference and Exhibition on Integration and Packaging of MEMS, NEMS, and Electronic Systems collocated with the ASME 2005 Heat Transfer Summer Conference
  • Advances in Electronic Packaging, Parts A, B, and C
  • San Francisco, California, USA, July 17–22, 2005
  • Conference Sponsors: Heat Transfer Division and Electronic and Photonic Packaging Division
  • ISBN: 0-7918-4200-2 | eISBN: 0-7918-3762-9
  • Copyright © 2005 by ASME

abstract

A detailed evaluation of modeling techniques used to incorporate a complex component level steady-state thermal model of a 32-pin SSOP package in a system level simulation is described. The device is an Application Specific IC designed for the present system, intended for use in a demanding automotive environment. The paper discusses the development of a compact model, used to enable the incorporation into a system level model with reasonable computational detail. The methodology involves a preliminary system level thermal analysis to estimate the ambient conditions in the vicinity of the device, followed by a detailed model of the device analyzed for various boundary conditions. A simplified compact model of the device is developed and validated against the detailed model. The compact model is shown to be accurate in the prediction of peak temperature in the package and boundary condition independent within realistic extremes of the operating environment. The fact that a compact model may not match the more detailed model at all points in the package is scrutinized in the context of correlation of the model to experimental results. The study highlights the significance of board-level conductivity enhancement and thermal vias under the package in reduction of package temperature.

Copyright © 2005 by ASME

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